The performance of amplifiers is heavily affected by variations in Process, Voltage, and Temperature (PVT). In CMOS technologies, the so-called constant-gm circuit [1] (gm=transconductance), illustrated in FIG. 1, is traditionally employed to partly compensate those variations. FIG. 1 shows an electronic biasing circuit with a current mirror CM1, a transistor pair TP1 and a resistor element Rb. The current mirror CM1 and transistor pair TP1 in FIG. 1 are implemented with MOSFETs.
The current mirror CM1 comprises two PMOS transistors M3, M4 connected in a well known current mirror arrangement, such that a current I1 flowing from a source to a drain of transistor M3 is substantially equal to a current I2 flowing from a source to a drain of transistor M4. Here, it is observed that the term “substantially” means “as close as possible to” within the error introduced by the finite output resistance of the MOSFETs, and within any possible manufacturing tolerances. This applies throughout the entire specification.
The gate of transistor M3 is connected to its drain. So, transistor M3 is diode connected. The sources of transistors M3, M4 are connected together to a power supply voltage VS.
The transistor pair TP1 comprises two NMOS transistors M1, M2. The gate of transistor M1 is connected to its drain. So, transistor M1 is diode connected. The gate and drain of transistor M1 are connected to the drain of transistor M4 of current mirror CM1. The source of transistor M1 is connected to ground voltage VGR, or, worded more generally, a supply reference voltage. The current through transistor M1 is indicated by I2′.
The gate of transistor M2 is connected to the gate of transistor M1. The source of transistor M2 is connected to one side of a resistor element Rb whereas the other side of the resistor element Rb is connected to ground voltage VGR. The drain of transistor M2 is connected to the drain of transistor M3. The current through transistor M2 is indicated by I1′.
Ideally, in the circuit of FIG. 1, because of the presence of current mirror CM1, the following relation should apply:I1=I2=I1′=I2′Transistors M1, M2, and resistor element Rb define the currents I1, I2, I1′, I2′ of this circuit in the non-trivial (non-zero) solution (a startup circuit—not shown in FIG. 1—is typically forcing the non-trivial solution to prevail). First order analysis with the well-known quadratic MOSFET model [1] shows that the transconductance of the MOSFETs is inversely proportional to the resistance Rb. The circuit generates a bias voltage Vg at the common node between the drain of transistor M4 and the drain/gate of transistor M1. This output voltage Vg is, for instance, used to bias gate terminals of MOSFETs in amplifiers, or other electronic circuits that need constant transconductance across PVT variations.
Some disadvantages of the circuit shown in FIG. 1 are:                1. The complex behavior of MOSFETs renders this circuit incapable of tracking the PVT variations in actual applications. Even transistor M1 (in FIG. 1) does not exhibit a constant transconductance across PVT variations.        2. The generation of only the bias voltage Vg is not enough to mirror the biasing conditions to other MOSFETs in other circuits connected to bias voltage Vg, potentially leading to significant errors in the definition of the current of the other circuit to be biased by the constant-gm circuit. The uncertainty in the definition of the transconductance is even higher.        